The re-use of circuit design information has become an important trend in the integrated circuit design industry. Large modern integrated circuit designs are increasingly created by assembling a number of previously-designed circuit portions, in an effort to reduce design turnaround times. Schematic and layout information for such circuit portions may be exchanged or licensed as design intellectual property. The successfulness of this trend thus depends on the amount of new design effort required to optimize and verify the performance of a new integrated circuit.
Verification is an important step in the process of designing and creating an electronic product. Verification helps ensure that the electronic design will work for its intended purpose, and is usually performed at several stages of the electronic design process. Circuit designers and verification engineers use different methods and analysis tools to optimize circuit designs, including simulation. Simulation verifies a design by monitoring computed behaviors of the design with respect to test stimuli. Circuit performance measurements may be performed by a post-simulation engine that evaluates simulated circuit waveforms, to save time. A variety of commercially offered software programs are available for circuit simulation. A circuit description used by a simulator is generally referred to as a netlist.
Flattening the description of a large composite circuit design into a single netlist and then simulating the entire new circuit design often takes too much memory and CPU time to be practical. As a result, circuit designers instead typically perform separate simulations, verifications, and optimizations on individual circuit blocks. Each circuit block may be simultaneously analyzed via a separate processor, to reduce the overall duration of this divide-and-conquer process.
Such parallel processing first requires dividing or partitioning of the integrated circuit into separate circuit blocks. These blocks may or may not match or closely correspond to the previously-designed circuit portions used for initial circuit construction. While partitioning by logical hierarchy may seem to be a good initial approach, it may be complicated by the possibility that parts of different blocks may operate under different clock domains in the new design. Critical timing paths may also span multiple blocks. Some initial circuit designs thus simply may not have a good logical hierarchy that lends itself to good partitioning.
Further, circuit pin assignment, floorplanning, and initial routing may be required to generate reasonably useful partitions for analysis. Layout tools may move and intertwine initially distinct block boundaries together to some extent, to reduce overall chip area. The boundaries of a logical hierarchy may thus not be clearly relatable to the boundaries of a physical hierarchy. Numerous time-consuming difficulties in dividing the integrated circuit for parallel processing can seriously limit design throughput capacity.
After partitioning, circuit designers typically allocate a portion of an overall full-chip timing budget to particular partitions, to generate block-level timing constraints. Such a priori budgeting may be non-optimal and even arbitrary. Timing budget quality is important when performing block-level optimization however, as a significant amount of repetitive analysis may result as timing constraints and budgets are adjusted between various interacting partitions.
Further, if each partition is optimized to meet its own functional goals and budget constraints without considering the goals and constraints of other partitions, changes to a particular partition may adversely impact the top level circuit's overall performance. In other words, a number of local partition optimizations may not necessarily lead to a fast global optimization of the full circuit design. Convergence problems with the overall currently used integrated circuit optimization process are therefore not unusual.
Thus, a need exists for an improved approach to circuit design optimization that avoids the bottlenecks and problems of the current design approach. Accordingly, the inventors have developed a novel methodology to help circuit designers optimize their large modern circuit designs.